Field Effect Transistor Structure Having Notched Mesa

ABSTRACT

A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.

TECHNICAL FIELD

This disclosure relates generally to Field Effect Transistor (FET)Structures and more particularly to FET structures having reduced gateparasitics.

BACKGROUND

As is known in the art, as the frequency of FET (Field EffectTransistor) operation goes above 90 GHz toward THz range, both gate andchannel lengths of FETs are reduced to sub-80 nm range towards 20 nmaccording to recent publications. At these small geometries, parasiticresistance, inductance, and capacitance of the FETs significantly affectthe RF performance of the FET device, such as power, gain andefficiency. Most of attempts to increase the operating frequency of FEThave focused on using smaller gate length and width, and narrow channel.

More particularly, a FET according to the PRIOR ART is shown in FIGS.1A-1C. Here, a semi-insulating, highly resistive, substrate, such asSiC, has formed on the upper surface thereof a mesa shaped semiconductorstructure, here for example a Group III-V structure, here, for example,a GaN structure. More particularly, III-V based structures such asGaN-based transistors use electrons formed between two different bandgapmaterials, for example, AlGaN and GaN. Formed in ohmic contact withsource and drain regions of the upper surface of the mesa are source anddrain electrodes, as shown. Disposed between the source and drainelectrodes is a gate electrode in Schottky contact with an upper surfaceof the mesa (a gate region) disposed between the source and drainregions. The gate electrode is used to control a flow of carriers (holesand electrons) in an active region of the mesa though the active region(sometimes herein referred to as the gate channel region) between thesource and drain regions. It is noted that the regions outside of themesa area, called ‘off mesa area’. The off mesa area, as noted above, issemi-insulating highly resistive area. The Effective gate width (theactive region) is the length of the gate electrode is the region closestto the source and drain regions (the gate channel region) and it is thisgate channel region that contributes to the conduction of transistor. Asthe gate channel width (the distance between the source and drain) getsnarrower to reduce the electron transfer time for high frequencyoperation, the contribution of the carriers in the gate channel regiongets stronger. From the prior art it is noted that the total gate lengthextends beyond the gate channel length even though the most of carrierconduction occurs along the gate channel length; however, the portionsof the gate electrode extending beyond the gate channel region generateparasitic gate resistance, inductance, and capacitance and therebycontribute negatively for high frequency operation.

Next, it is noted that the source electrode is disposed within opposingsidewalls of the mesa structure, the drain electrode is disposed withinthe opposing sidewalls in ohmic contact with a drain region of the mesa,and the gate electrode is disposed within opposing walls of the gateregion of the mesa and that the mesa is rectangular shape. Further, itis noted that the source electrode has an inner edge extending betweenends SOURCE EDGE 1, SOURCE is EDGE 2 (FIG. 1A) thereof proximate thegate electrode that extends along a direction parallel to the gateelectrode; and, likewise the drain electrode has an inner edge extendingbetween ends DRAIN EDGE 1, DRAIN EDGE 2 (FIG. 1) thereof proximate thegate electrode that extends along a direction parallel to the gateelectrode. The lengths of the inner edges of the source and drainelectrodes are equal. The gate electrode extends beyond the ends ofSOURCE EDGE 1, SOURCE EDGE 2 of the inner edge of the source electrodeand thus also beyond the ends of DRAIN EDGE 1, DRAIN EDGE 2 of the inneredge of the drain electrode. The active region (gate channel) extendsbetween ends DRAIN EDGE 1 (or SOURCE EDGE 1) and DRAIN EDGE 2 (or SOURCEEDGE 2) (FIG. 1A). As noted above, the total gate electrode lengthextends beyond the active region (gate channel length), even though themost of carrier conduction occurs along the gate channel length,generates unwanted parasitic gate resistance, inductance, andcapacitance and thereby contributes negatively for high frequencyoperation of the FET.

SUMMARY

In accordance with the present disclosure, a Field Effect Transistorstructure is provided having: a semi-insulating substrate; asemiconductor mesa structure disposed on the substrate and having anotch in an outer sidewall of the mesa structure; a source electrodedisposed within the opposing sidewalls in ohmic contact with a sourceregion of the mesa structure; a drain electrode disposed within theopposing sidewalls in ohmic contact with a drain region of the mesastructure; and a gate electrode, having an inner portion disposedbetween, and laterally of, the source electrode and the drain electrodeand in Schottky contact with the mesa structure, extendinglongitudinally towards the notch and having outer portions extendingbeyond the mesa structure and over portions of the substrate outside ofthe mesa structure.

In one embodiment, the mesa structure includes a pair of notches projectinwardly towards each other and the inner portion of the gate extendslongitudinally between the pair of notches.

With such an arrangement, the gate parasitics of the prior art arereduced by the formation of the notches in the mesa structure becauseextra gate length on top of the active region of the mesa structure iseliminated and the gate tab (or pad) disposed on the substrate off ofthe mesa structure is able to be positioned closer to active innerportion of the gate. With a multi-fingered gate structure, as the numberof gate fingers increases, the parasitic components are multiplied andtherefore the disclosed. FET structure significantly improves theperformance of FETs with multiple gate fingers at high operatingfrequency.

The details of one or more embodiments of the disclosure are set forthin the accompanying drawings and the description below. Other features,objects, and advantages of the disclosure will be apparent from thedescription and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIGS. 1A-1C are plan, and cross sectional views of a Field EffectTransistor structure according to the PRIOR. ART, where the crosssectional views in FIGS. 1B and 1C are taken along lines 1B-1B and1C-1C, respectively, in FIG. 1A;

FIGS. 2A-2B are plan, and cross sectional views of a Field EffectTransistor structure according to the disclosure, where the crosssectional views in FIGS. 2B and 2C are taken along lines 2B-2B and2C-2C, respectively, in FIG. 2A;

FIG. 3 is a plan view of the Field Effect Transistor structure of FIG.1A disposed in a side-by-side relationship with the Field EffectTransistor structure of FIG. 2B to compare the two Field EffectTransistor structures; and

FIG. 4 is a plan view of a multi-gate embodiment of a Field EffectTransistor structure according to the disclosure.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Referring now to FIGS. 2A-2C, a Field Effect Transistor structure 10 isshown having: a semi-insulating substrate 12, here for example, asemi-insulating, highly resistive, substrate, such as SiC, GaAs, andInP; a semiconductor mesa structure 14, here for example, a Group III-Vstructure such as a GaN structure, disposed on the upper surface 16 ofthe substrate 12 and having a pair of notches 18 in opposing outersidewalls 20 of the mesa structure 14; a source electrode 22 disposedwithin the opposing sidewalls 20 in ohmic contact with a source region24 (FIG. 2C) of the mesa structure 14 under the source electrode 22; adrain electrode 26 disposed within the opposing sidewalls 20 in ohmiccontact with a drain region (not shown) under the drain electrode 26 ofthe mesa structure 14; and a gate electrode 28, having an inner portion28 a disposed between, and laterally of, the source electrode 22 and thedrain electrode 26 and in Schottky contact with the portion of the mesastructure 14 under the inner portion of the gate electrode 28 a,extending longitudinally between the pair of notches 18 and having outerportions 28 b extending beyond the mesa structure 14 and over portionsof the upper surface 16 of substrate 12 outside of the mesa structure 14(“off-mesa”). Thus, here the mesa structure 14 includes a pair ofnotches 18 which project inwardly towards each other and the innerportion 28 a of the gate 28 extends longitudinally between the pair ofnotches 18. It is noted that here the notches 18 are v-shaped notches.It should be understood, however, that the notches 18 may be of adifferent shapes and includes, for example, any shaped indentation orgroove in the sidewalls 20 of the mesa structure 14, including, forexample, a rounded indentation, a square or rectangular indentation.

Further, it is noted that the source electrode 22 has an inner edge 23extending between ends SE 1 and SE2 (FIG. 2A) thereof proximate theinner portion 28 a of gate electrode 28; and, likewise the drainelectrode 26 has an inner edge 27 extending between ends DE1, DE2 (FIG.2A) thereof proximate the inner portion 28 a of gate electrode 28. Here,the lengths of the inner edges 23, 27 of the source and drain electrodes22, 26 are equal. The gate electrode 28 extends beyond the ends SE1, SE2of the inner edge 23 of the source electrode 22 and thus also beyond theends DE1, DE2 of the inner edge 27 of the drain electrode 26. The activeregion (gate channel) 29 in under the inner portion 28 a of the gateelectrode 28 and extends between ends DE1 (or SE1) and DE2 (or SE2)(FIG. 2A).

It is noted that the inner portion 28 a of the gate electrode 28 iselongated and the source electrode 22 and the drain electrode 26 arehere also elongated along directions parallel to the direction of theelongated inner portion 28 a of the gate electrode 28. It is also notedthat the source electrode 22 is within opposing outer portions of thesidewalls 20 of the mesa structure. 14 separated a length L_(ms)measured along the top surface of the mesa; the drain electrode iswithin opposing portions of the sidewalls 20 separated a length L_(md)measured along the top surface of the mesa; and the inner portion 28 aof the gate electrode 28 is within the pair of notches 18, the notchesbeing separated a length L_(mg) measured along the top surface of themesa; where L_(mg) is less than either one of the lengths L_(md) orL_(ms); it here being noted that length L_(md) equals length L_(ms). Itis noted that all three lengths are measured along directions parallelto the direction of the elongated inner portion 28 a of the gateelectrode 28. One end of the inner portion 28 a of the gate electrode 28terminates in a gate pad 28 p and a portion 28 p′of the gate pad 28 p isdisposed within a portion of one of the pair of notches 18, here thenotch 28 on the right hand side of mesa structure 14 in FIG. 2A. Thegate pad 28 p is wider than the inner region 28 a of the gate electrode28.

Referring now to FIG. 3, a comparison is shown between the plan view ofa mesa structure with a pair of opposing notches (the upper portion ofFIG. 3) and a mesa structure without a pair of opposing notches (thelower portion of FIG. 3). It is noted that the length of the gateelectrode between the end of the active gate region and the gate pad onthe right hand side of FIG. 3 with the notch is less than the length ofthe gate electrode between the end of the active gate region and thegate pad without the notch by a difference in length DIFF1. Similarly,it is noted that the length of the gate electrode between the end of theactive gate region and the left hand end of the gate electrode with thenotch is less than the length of the gate electrode between the end ofthe active gate region and the left hand end of the gate electrodewithout the notch by a difference in length DIFF2. Thus, the gateparasitics are reduced by the formation of the notches in the mesastructure because extra gate length on top of the active region of themesa structure is eliminated and the gate tab (or pad) disposed on thesubstrate off of the mesa structure is able to be positioned closer toactive inner portion of the gate.

Referring now to FIG. 4, a multi-fingered gate structure, here havingtwo gate fingers, it being understood that more than two gate fingersmay be used, of the FET of FIGS. 2A-2C is shown. Here, the sourceelectrode is connected to a ground plane on the bottom surface of thesubstrate with a conductive via passing vertically through the mesastructure and the underlying portion of the substrate. It is noted thatas the number of gate fingers increases, the parasitic components aremultiplied and therefore the disclosed FET structure significantlyimproves the performance of FETs with multiple gate fingers.

A number of embodiments of the disclosure have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the disclosure.Accordingly, other embodiments are within the scope of the followingclaims.

1. A Field Effect Transistor structure, comprising: a substrate; asemiconductor mesa structure disposed on a portion of a surface of thesubstrate, the mesa structure having a notch in an outer sidewall of themesa structure; a source electrode in ohmic contact with a source regionof the mesa structure; a drain electrode in ohmic contact with a drainregion of the mesa structure; a gate electrode, having an inner portionand an outer portion, the inner portion being disposed over an activeregion in the mesa and disposed between the source region and the drainregion and in Schottky contact with the active region in the mesastructure, the inner portion extending along the direction parallel tothe surface of the substrate towards the notch, the outer portionextending beyond the mesa structure and over portions of the substrateoutside of the mesa structure; and wherein the notch projects along adirection parallel to the surface of the substrate from the outersidewall toward, and terminating prior to, the active region in the mesastructure.
 2. The Field Effect Transistor structure recited in claim 1wherein the mesa has an outer second sidewall opposing thefirst-mentioned outer sidewall and wherein the second outer sidewall hasa second notch therein project inwardly towards the first-mentionednotch and wherein the active region is disposed between the firstmentioned notch and the second notch.
 3. The Field Effect Transistorstructure recited in claim 1 wherein: the source electrode is disposedwithin opposing outer sidewalls of a second portion of the mesastructure, the opposing outer sidewalls of the second portion of themesa structure being separated a length L_(ms) measured along a topsurface of the mesa; the drain electrode is disposed within opposingouter sidewalls of a third portion of the mesa structure, the opposingouter sidewalls of the third portion of the mesa structure beingseparated a length L_(md) measured along a top surface of the mesa;wherein outer sidewall of the mesa structure having the notch and anouter sidewall opposing the outer sidewall having the notch areseparated a length L_(mg) measured along a top surface of the mesastructure; where L_(mg) is less than either L_(md) or L_(ms).
 4. TheField Effect Transistor structure recited in claim 2 wherein: the sourceelectrode is disposed with opposing outer sidewalls of a second portionof the mesa structure, the opposing outer sidewalls of the secondportion of the mesa structure are e separated a length L_(ms); the drainelectrode is disposed within opposing outer sidewalls of a third portionof the mesa structure, the opposing outer sidewalls of the third portionof the mesa structure being separated a length L_(md); the opposingsidewalls of the mesa structure having the notches have a separation alength L_(mg); where L_(mg) is less than either L_(md)or L_(ms).
 5. TheField Effect Transistor structure recited in claim 1 wherein the outerportion of the gate electrode terminates in a gate pad and wherein aportion of the gate pad is disposed within a portion of the notch. 6.The Field Effect Transistor structure recited in claim 5 wherein thegate pad is wider than the inner portion of the gate electrode.
 7. TheField Effect Transistor structure recited in claim 2 wherein the outerportion of the gate electrode terminates in a gate pad and wherein aportion of the gate pad is disposed within a portion of the notch. 8.The Field Effect Transistor structure recited in claim 7 wherein thegate pad is wider than the inner portion of the gate electrode.
 9. TheField Effect Transistor structure recited in claim 3 wherein the outerportion of the gate electrode terminates in a gate pad and wherein aportion of the gate pad is disposed within a portion of the notch. 10.The Field Effect Transistor structure recited in claim 9 wherein thegate pad is wider than the inner portion of the gate electrode.
 11. TheField Effect Transistor structure recited in claim 1 wherein the mesastructure is a Group III-V structure.
 12. The Field Effect Transistorstructure recited in claim 2 wherein the mesa structure is a Group III-Vstructure.
 13. The Field Effect Transistor structure recited in claim 3wherein the mesa structure is a Group structure.
 14. A Field EffectTransistor structure, comprising: a substrate; a semiconductor mesastructure disposed on the substrate; a source electrode, disposed withinopposing sidewalls of a first portion of the mesa structure, in ohmiccontact with a source region of the mesa structure, opposing sidewallsof the first portion of the mesa structure being separated a lengthL_(ms) measured along a top surface of the mesa; a drain electrode,disposed within the opposing sidewalls of a second portion of the mesastructure, in ohmic contact with a drain region of the mesa structure,opposing sidewalls of the second portion of the mesa structure beingseparated a length L_(md) measured along a top surface of the mesa; agate electrode, having: an inner portion disposed between the sourceelectrode and the drain electrode and in Schottky contact with the mesastructure, the gate electrode extending longitudinally across the mesastructure and, outer portions extending beyond the mesa structure andover portions of the substrate outside of the mesa structure, the innerportion of the gate being within opposing sidewalls of a third portionof the mesa structure, the opposing sidewalls of the third portion ofthe mesa structure having a separation a length L_(mg) measured along atop surface of the mesa; where L_(mg) is less than either L_(md) orL_(ms).
 15. A Field Effect Transistor structure, comprising: asubstrate; a semiconductor region disposed on a surface of thesubstrate, a first portion of the semiconductor region having opposingsides, such semiconductor region having a notch in one of the opposingsides of the first portion of the semiconductor region; a sourceelectrode disposed within the opposing sides of a second portion of thesemiconductor, in ohmic contact with a source region of thesemiconductor region; a drain electrode, disposed within the opposingsides of a third portion of the semiconductor region, in ohmic contactwith a drain region of the semiconductor region; a gate electrode,having an inner portion disposed on an active region in thesemiconductor region between the source electrode and the drainelectrode and in Schottky contact with the active region of thesemiconductor region, extending longitudinally along a predetermineddirection towards, and terminating prior to, the active region, theouter portions extending beyond an outer periphery of the semiconductorregion and over portions of the substrate outside of the semiconductorregion; and wherein the notch extends, along a direction parallel to thesurface of the substrate and parallel to the predetermined direction,from the outer periphery of the semiconductor region towards an innerportion of the semiconductor region.
 16. The Field Effect Transistorstructure recited in claim 15 wherein the semiconductor region has anadditional notch in a second one of the opposing sides of the firstportion of the semiconductor region; and wherein the first-mentionednotch and the additional notch project inwardly towards each other andwherein the inner portion of the gate extends longitudinally between thefirst-mentioned notch and the additional notch.
 17. The Field EffectTransistor structure recited in claim 15 wherein: the opposing outersides of the second portion of semiconductor region are separated alength L_(ms) measured along a top surface of the semiconductor region;the opposing sides of the third portion of the semiconductor region areseparated a length L_(md) measured along a top surface of thesemiconductor region; the opposing sides of the first portion of thesemiconductor region are separated length L_(mg) measured along a topsurface of the semiconductor region; where L_(mg) is less than eitherL_(md) or L_(ms).
 18. The Field Effect Transistor structure recited inclaim 16 wherein: the opposing sides of the second portion of thesemiconductor region are separated a length L_(ms); the opposing sidesof the third portion of the semiconductor region are separated a lengthL_(md); the inner portion of the gate is disposed between thefirst-mentioned notch and the additional notch a length L_(mg); whereL_(mg) is less than either on of L_(md) or L_(ms).
 19. The Field EffectTransistor structure recited in claim 15 wherein the outer portion ofthe gate electrode terminates in a gate pad and wherein a portion of thegate pad is disposed within a portion of the notch.
 20. The Field EffectTransistor structure recited in claim 19 wherein the gate pad is widerthan the inner portion of the gate electrode.
 21. The Field EffectTransistor structure recited in claim 16 wherein the outer portion ofthe gate electrode terminates in a gate pad and wherein a portion of thegate pad is disposed within a portion of the first-mentioned notch. 22.The Field Effect Transistor structure recited in claim 21 wherein thegate pad is wider than the inner portion of the gate electrode.
 23. TheField Effect Transistor structure recited in claim 17 wherein the outerportion of the gate electrode terminates in a gate pad and wherein aportion of the gate pad is disposed within a portion of the notch. 24.The Field Effect Transistor structure recited in claim 23 wherein thegate pad is wider than the inner portion of the gate electrode.
 25. TheField Effect Transistor structure recited in claim 15 wherein thesemiconductor region is a Group III-V structure.
 26. The Field EffectTransistor structure recited in claim 16 wherein the semiconductorregion is a Group III-V structure.
 27. The Field Effect Transistorstructure recited in claim 17 wherein the semiconductor region is aGroup III-V structure.
 28. A Field Effect Transistor structure,comprising: a substrate; a semiconductor region disposed on thesubstrate; a source electrode disposed on a first portion of thesemiconductor region in ohmic contact with a source region of thesemiconductor region, the first portion of the semiconductor regionhaving opposing ends separated a length L_(ms) measured along a topsurface of the semiconductor region; a drain electrode disposed on asecond portion of the semiconductor region in ohmic contact with a drainregion of the semiconductor region, the second portion of thesemiconductor region having opposing ends separated a length L_(md)measured along a top surface of the semiconductor region; a gateelectrode, having an inner portion disposed on a third portion of thesemiconductor region between the source electrode and the drainelectrode and in Schottky contact with the semiconductor regionextending longitudinally across the semiconductor region and havingouter portions extending beyond the semiconductor region and overportions of the substrate outside of the semiconductor region, the thirdportion of the semiconductor region having opposing ends separatedseparation a length L_(mg) measured along a top surface of thesemiconductor region; where L_(mg) is less than either on of L_(md) orL_(ms).
 29. The Field Effect Transistor structure recited in claim 15wherein the inner portion of the gate electrode has a width along adirection perpendicular to predetermined direction and wherein the notchhas a width, along the predetermined direction, at the outer peripheryof the semiconductor region greater than the width of the inner portionof the gate electrode.
 30. A Field Effect Transistor structure,comprising: a substrate; a semiconductor region disposed on a portion ofa surface of the substrate, the semiconductor region having a notch inan outer periphery of the semiconductor region, the notch projectingfrom the outer periphery toward, and terminating prior to, an activeregion in the semiconductor region, an interior region of thesemiconductor region along a direction parallel to the surface of thesubstrate; a source electrode in ohmic contact with a source region ofthe semiconductor region; a drain electrode in ohmic contact with adrain region of the semiconductor region; a gate electrode, having aninner portion and an outer portion, the inner portion being disposed inthe active region between the source electrode and the drain electrodeand in Schottky contact with the active region in the semiconductorregion, the inner portion extending along the direction parallel to thesurface of the substrate towards the notch, the outer portion extendingbeyond the semiconductor region and over portions of the substrateoutside of the semiconductor region.
 31. The Field Effect Transistorstructure recited in claim 30 wherein the notch passes through thesemiconductor region from a top surface of the semiconductor region tothe surface of the substrate.
 32. The Field Effect Transistor structurerecited in claim 30 wherein the inner portion of the gate electrode hasa width along a direction perpendicular to the direction parallel to thesurface of the substrate and wherein the notch has a width, along thedirection perpendicular to the direction parallel to the surface of thesubstrate, at the outer periphery of the semiconductor region greaterthan the width of the inner portion of the gate electrode.
 33. A FieldEffect Transistor structure, comprising: a substrate; a semiconductorregion disposed on a surface of the substrate, the semiconductor regionhaving a notch in a sidewall of the semiconductor region; a sourceelectrode in ohmic contact with a source region of the semiconductorregion; a drain electrode in ohmic contact with a drain region of thesemiconductor region; a gate electrode, having: an inner portiondisposed on an active region in the semiconductor region between thesource electrode and the drain electrode and in Schottky contact withthe active region; an outer portion extending beyond the sidewall of thesemiconductor region and over portions of the substrate outside of thesemiconductor region and into the notch; and a gate pad disposed in thenotch and connected to the outer portion of the gate electrode.